1. Field of the Invention
The present invention relates to the field of one-time programmable (OTP) non-volatile memory cells, which can keep a programmed state even after the circuit is powered off. The present invention more specifically relates to such a memory cell comprising an oxide capacitor.
2. Discussion of the Related Art
An example of application of OTP cells is the formation of redundancy elements, which are generally provided in memories made in the form of one or several integrated circuit arrays, to functionally replace a defective memory element. The function of the OTP cells is to program the shifting of the memory rows or columns upon use of a redundancy element to overcome the failure of a column or a row of the array.
In this type of application, either elements fusible by a laser, for example, or OTP memory cells of EEPROM type or of the floating-gate transistor type are used. All these conventional structures have the major disadvantage of not being compatible with simple CMOS manufacturing methods. In particular, non-volatile EPROM-type memory cells require two gate oxide thicknesses while a standard CMOS manufacturing method only uses one.
In a standard CMOS method, after the forming of source and drain regions of P-channel and N-channel MOS transistors in a silicon substrate, a single oxide layer (generally, silicon oxide) and a single polysilicon layer are deposited to form the transistor gates before the metallization levels.
Polysilicon fusible structures are also known, however, which require a strong programming current to obtain the fusion (on the order of 100 mA).
The category of OTP cells to which the present invention applies is generally called an xe2x80x9canti-fusexe2x80x9d structure since the unprogrammed state of the cell is a state of isolation of two electrodes and its programmed state is a state of current flow. The cells are, more specifically, formed of a capacitor formed of an oxide thickness likely to be made conductive (to break down) after application of an overvoltage between the two electrodes of the capacitor.
A problem which arises in the making of such an oxide breakdown structure with a standard CMOS method is linked to the switching of the high voltage required to break down the capacitors. Indeed, standard transistors cannot switch this high voltage without being, themselves, in a breakdown state.
For example, in a technology where the minimum dimension of a mask pattern is 0.25 xcexcm, the CMOS circuit supply voltage generally is on the order of 2.5 V, while an oxide breakdown OTP cell requires on the order of 10 V for an oxide having a thickness on the order of 5 nm, which is the usual thickness of the gate oxide in this technology.
While such a 10-V voltage is generally available on the integrated circuit boards for which the memory integrated circuits are intended, this voltage is not compatible with addressing selection structures and memory input-output stages, the operating voltage of which is linked to the CMOS method used.
U.S. Pat. No. 4,943,538 discloses an anti-fuse memory cell wherein several oxide levels are necessary. Accordingly, this memory cannot be implemented without additional steps with respect to a conventional CMOS process using only one oxide level.
U.S. Pat. No. 5,324,681 and European Pat. Application 0528417 disclose anti-fuse memory cells using a DRAM manufacturing method with two oxides (the CMOS oxide and the oxide of the DRAM capacitors that is thinner so as to be breakable with a conventional transistor). It is accordingly necessary to add steps with respect to a conventional CMOS process.
The present invention aims at providing a novel OTP memory cell of oxide breakdown type, which is compatible with a simple CMOS manufacturing method. In particular, the present invention aims at providing a solution which requires a single gate oxide level in the manufacturing method.
The present invention also aims at making it possible for the memory cells to be manufactured with no additional step with respect to a conventional CMOS method.
Thus, the present invention provides an OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region that is deeper and less doped than the source.
According to an embodiment of the present invention, this series association is connected between two terminals of application of a supply voltage.
According to an embodiment of the present invention, a first electrode of the capacitor is formed by said region.
According to an embodiment of the present invention, the capacitor is formed in an oxide level constitutive of transistor gates.
According to an embodiment of the present invention, a second electrode of the capacitor is adapted to receiving, in read mode, a relatively low voltage and, in programming, a relatively high voltage.
According to an embodiment of the present invention, the transistor and the capacitor are sized so that, in a programming cycle and for an unselected cell, the voltage across the capacitor remains smaller than its breakdown voltage when the currents in the capacitor and in the transistor are balanced.
According to an embodiment of the present invention, the transistor is sized to limit the current in a selected cell while allowing a breakdown of the oxide constitutive of the capacitor.
The invention also provides a method for manufacturing OTP memory cells of the anti-fuse type wherein the unbalanced drain regions of the programming transistors of a first channel type are formed simultaneously with the wells aimed at receiving MOS transistors of a second channel type.
The foregoing features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.